Journal of the Microelectronics and Packaging Society

With the increasing demand for high-performance computing and bandwidth, high bandwidth memory (HBM)-based multi-chip integrated packaging is emerging as a key technology for next-generation semiconductors. However, thermomechanical stress generated during the assembly process can induce package warpage, leading to decreased reliability. To address this issue, glass substrates with tunable coefficients of thermal expansion (CTE) are gaining attention as promising alternatives. In this study, HBM chips in various quantities (9, 15, and 25) were mounted on glass substrates using flip chip, thermal-compression bonding (TCB) followed by molded underfill (MUF) processes, employing different layout configurations. Warpage behavior was quantitatively analyzed using digital image correlation (DIC). Experimental results showed that warpage values of 2,435.7 µm and 2,601.6 µm were observed for 9 and 15 chips, respectively, whereas a uniformly arranged 25-chip configuration exhibited significantly reduced warpage of 1,262.5 µm. These findings demonstrate that uniform chip arrangement plays a critical role in minimizing warpage and provides meaningful design guidance for future glass-based multi-chip package architectures.

Keywords Glass, Thermo-compression bonding (TCB), Molded underfill (MUF), Flip chip bonding, Warpage