2024

Vol.31 No.3

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  • Journal of the Microelectronics and Packaging Society
  • Volume 30(1); 2023
  • Article

Review

Journal of the Microelectronics and Packaging Society 2023;30(1):42-48. Published online: May, 11, 2023

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DOI : doi.org/10.6117/kmeps.2023.30.1.042

Plasma Application Technology of FOWLP (Fan-out Wafer Level Packaging) Process

  • Se Yong Park1, Seong Eui Lee1, Hee Chul Lee1, Sung Yong Kim2, Nam Sun Park3, and Kyoung Min Kim1,†
    1 Dept. of Advanced Materials Eng., Tech University of Korea, 237. Sangidaehak-ro, Siheung-si, Gyeonggi-do, Korea, 2Dept. of Electronics Eng., Tech University of Korea, 237. Sangidaehak-ro, Siheung-si, Gyeonggi-do, Korea, 3 JESAGI HANKOOK LTD., 17, MTV 25-ro58beon-gil, Siheung-si, Gyeonggi-do, Korea
Corresponding author E-mail: kkm386@tukorea.ac.kr
Abstract

Recently, there has been an increasing demand for performance improvement and miniaturization in response to the growing variety of signals and power demands in many industries such as mobile, IoT, and automotive. As a result, there is a high demand for high-performance chips and advanced packaging technologies that can package such chips. In this context, the FOWLP process technology is a suitable technology, and this paper discusses the plasma application technologies that are being used and studied to improve the shortcomings of this process. The paper is divided into four parts, with an introduction and case studies for each of the plasma application technologies used in each part.

Keywords FOWLP(Fan-out wafer level packaging), Plasma, Packaging, PCB(Printed Circuit Board)

REFERENCES
  • J. Lau, M. Li, N. Fan, E. Kuah, Z. Li, K.H. Tan, T. Chen, I. Xu, M. Li, Y.M. Cheung, and W. Kai, "Fan-out wafer-level packaging (FOWLP) of large chip with multiple redistribution layers (RDLs)", J. Microelectron. Electron. Packag., 14(4), 123-131 (2017). https://doi.org/10.4071/imaps.522798
  • V. S. Rao, C. T. Chong, D. Ho, D. M. Zhi, C. S. Choong, L. P. Sharon, D. Ismael, and Y. Y. Liang, "Development of high density fan out wafer level package (HD FOWLP) with multilayer fine pitch RDL for mobile applications", In 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 1522-1529 (2016).
  • T. Braun, M. Topper, K. F. Becker, M. Wilke, M. Huhn, U. Maass, I. Ndip, R. Aschenbrenner, and K. D. Lang, "Opportunities of fan-out wafer level packaging (FOWLP) for RF applications", In 2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 35-37 (2016).
  • J. H. Lau, M. Li, D. Tian, N. Fan, E. Kuah, W. Kai, M. Li, J. Hao, Y.M. Cheung, Z. Li, and K. H. Tan, "Warpage and thermal characterization of fan-out wafer-level packaging", IEEE Trans. Compon. Packaging. Manuf. Technol., 7(10), 1729-1738 (2017). https://doi.org/10.1109/TCPMT.2017.2715185
  • J. H. Lau, "Fan-out wafer-level packaging", Singapore: Springer Singapore, (2018).
  • J. H. Lau and J. H. Lau, "System-in-package (sip)", Semiconductor Advanced Packaging, 27-74 (2021).
  • T. Hwang, D. Oh, J. Kim, E. Song, T. Kim, K. Kim, J. Lee, and T. Kim, "The thermal dissipation characteristics of the novel system-in-package technology (ICE-SiP) for mobile and 3D high-end packages", In 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 614-619 (2019).
  • J. Chen, Y. Xie, D. Trombley, and R. Murugan, "System codesign of a 600V GaN FET power stage with integrated driver in a QFN system-in-package (QFN-SiP)", In 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 1221-1226 (2019).
  • W. Tian, C. Wang, Z. Zhao, and H. Cui, "Structures and materials of system-in-package: a review", Recent Pat. Mech. Eng., 14(1), 28-41 (2021). https://doi.org/10.2174/2212797613999200728190605
  • M. K. Shih, N. Y. Wu, W. H. Lai, T. Y. Chen, C. L. Kao, and C. P. Hung, "Board-Level Drop Impact Reliability Analysis of Dual-Side Molding System-in-Package (SiP) Modules", IEEE Trans. Electron Devices, 70(1), 215-221 (2022).
  • J. Li, M. Tsai, R. Chiu, E. He, A. Hsieh, M. F. Tsai, F. Chu, J. Y. Chen, S. Jian, S. Chen, and Y. P. Wang, "EMI shielding technology in 5G RF system in package module", In 2020 IEEE 70th electronic components and technology conference (ECTC), 931-937 (2020).
  • M. Tsai, R. Chiu, D. Huang, F. Kao, E. He, J. Y. Chen, S. Chen, J. Tsai, and Y. P. Wang, "Innovative packaging solutions of 3D double side molding with system in package for IoT and 5G application", In 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 700-706 (2019).
  • A. Garnier, L. Castagne, F. Greco, T. Guillemet, L. Marechal, M. Neffati, R. Franiatte, P. Coudrain, S. Piotrowicz, and G. Simon, "System in package embedding III-V chips by fan-out wafer-level packaging for RF applications", In 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 2016-2023 (2021).
  • L. Ding, X. C. Wei, Z. Y. Tang, J. Wen, L. Gao, and R. X. K. Gao, "Near-field scanning based shielding effectiveness analysis of system in package", IEEE Trans. Compon. Packaging. Manuf. Technol., 11(8), 1235-1242 (2021). https://doi.org/10.1109/TCPMT.2021.3096148
  • V. Goyal, X. Wang, V. Bertacco, and R. Das, "Neksus: An interconnect for heterogeneous system-in-package architectures", In 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 12-21 (2020).
  • Y. S. Shao, J. Clemons, R. Venkatesan, B. Zimmer, M. Fojtik, N. Jiang, B. Keller, A. Klinefelter, N. Pinckney, P. Raina, and S. G. Tell, "Simba: Scaling deep-learning inference with multichip-module-based architecture", In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 14-27 (2019).
  • N. C. Abrams, Q. Cheng, M. Glick, M. Jezzini, P. Morrissey, P. O'Brien, and K. Bergman, "Silicon photonic 2.5 D multichip module transceiver for high-performance data centers", J. Light. Technol., 38(13), 3346-3357 (2020). https://doi.org/10.1109/jlt.2020.2967235
  • B. Ramakrishnan, M. Tradat, Y. Hadad, K. Ghose, and B. Sammakia, "Characterization of Liquid Cooled Cold Plates for a Multi Chip Module (MCM) and their Impact on Data Center Chiller Operation", In 2019 IEEE 17th International Conference on Industrial Informatics (INDIN), 1, 1419-1424 (2019).
  • R. Meade, S. Ardalan, M. Davenport, J. Fini, C. Sun, M. Wade, A. W.-Gladstein, and C. Zhang, "TeraPHY: a high-density electronic-photonic chiplet for optical I/O from a multichip module", In 2019 Optical Fiber Communications Conference and Exhibition (OFC), 1-3 (2019).
  • G. Nan, Z. Xie, X. Guan, X. Ji, and D. Lin, "Constructal design for the layout of multi-chip module based on thermalflow-stress coupling calculation", Microelectron. Reliab., 127, 114417 (2021).
  • Y. C. Son, "Fan-out wafer-level packaging (FOWLP) 기술 동향", Electrical & Electronic Materials, 34(2), 4-11 (2021).
  • Z. Cai, Y. Ding, Z. Wu, Z. Zhang, Y. Su, and Z. Chen, "An All-Wet, Low Cost RDL Fabrication Process with Electroless Plated Seed/Barrier Layers", In 2021 IEEE International Interconnect Technology Conference (IITC), 1-4 (2021).
  • F. Franco, R. A. Dias, J. Gaspar, S. C. de Freitas, and P. P. Freitas, "Hybrid rigid-flexible magnetoresistive device based on a wafer level packaging technology for micrometric proximity measurements", IEEE Sens. J., 19(24), 12363-12368 (2019). https://doi.org/10.1109/jsen.2019.2938368
  • J. Zhao, "Plasma Applications for Wafer Level Packaging Part 1. In 2019 20th International Conference on Electronic Packaging Technology (ICEPT), 1-4 (2019).
  • G. Ezhilarasu, "Flexible, Heterogeneously Integrated microLED Displays in Elastomeric Substrates Using Fan-Out Wafer-Level Packaging", University of California, Los Angeles (2021).
  • P. Nimbalkar, P. Bhaskar, C. Blancher, M. Kathaperumal, M. Swaminathan, and R. Tummala, "Novel zero side-etch process for < 1μm package redistribution layers", In 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), 2168-2173 (2022).
  • C. K. Chung, M. Q. Tsai, P. H. Tsai, and C. Lee, "Fabrication and characterization of amorphous Si films by PECVD for MEMS", J. Micromech. Microeng., 15(1), 136 (2004).
  • J. H. Lau, "Redistribution-layers for fan-out wafer-level packaging and heterogeneous integrations", In 2019 China Semiconductor Technology International Conference (CSTIC), 1-10 (2019).
  • J. H. Lau, "2D, 2.1 D, and 2.3 D IC Integration. In Semiconductor Advanced Packaging", Singapore: Springer Singapore, 239-298 (2021).
  • F. Wang, Q. Liu, X. Wang, J. Li, G. Zhang, and R. Sun, "Nondestructive Laser Debonding of Designable Responsive and Buffer Layers for Wafer Level Packaging", In 2022 23rd International Conference on Electronic Packaging Technology (ICEPT), 1-4 (2022).
  • Y. M. Lin, W. L. Chiu, C. J. Chen, H. E. Ding, O. H. Lee, A. Y. Lin, R. S. Cheng, S. T. Wu, T. C. Chang, H. H. Chang, and W. C. Lo, "A novel multi-chip stacking technology development using a flip-chip embedded interposer carrier integrated in fan-out wafer-level packaging", In 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 1076-1081 (2021).
  • J. H. Lau, "Recent Advances and Trends in Multiple System and Heterogeneous Integration with TSV-Less Interposers", IEEE Trans. Compon. Packaging. Manuf. Technol. (2022).
  • C. Song and S. E. Kim, "Process and characterization of photo-definable organic-inorganic dielectric for wafer level packaging", Microsyst. Technol., 25, 4559-45655 (2019). https://doi.org/10.1007/s00542-019-04418-y
  • J. Dawes and M. L. Johnston, "Direct-Write 3D Printing of Interconnects for Fan-Out Wafer-Level Packaging", In 2022 IEEE International Conference on Flexible and Printable Sensors and Systems (FLEPS), 1-4 (2022).
  • M. J. Li, "DENSE 3D HETEROGENEOUS INTEGRATION USING SELECTIVE COBALT ALD DEPOSITION AND RECONSTITUTED TIERS (Doctoral dissertation", Georgia Institute of Technology (2021).
  • K. Son, S. Kim, C. Kim, G. Kim, Y. C. Joo, and Y. B. Park, "Effect of Ta/Cu Film Stack Structures on the Interfacial Adhesion Energy for Advanced Interconnects", J. Microelectron. Packag. Soc., 28(1), 39-46 (2021). https://doi.org/10.6117/KMEPS.2021.28.1.039
  • S. Dwarakanath, "Ultra-Low Dielectric Constant and UltraThin Polymer Dielectric Materials, Processes and Reliability for Ultra-High Bandwidth Computing Applications", Doctoral dissertation, Georgia Institute of Technology (2020).
  • I. Berbezier, M. Aouassa, A. Ronda, L. Favre, M.O.N.I.C.A. Bollani, R.O.M.A.N. Sordan, A. Delobbe, and P. Sudraud, "Ordered arrays of Si and Ge nanocrystals via dewetting of pre-patterned thin films", J. Appl. Phys., 113(6), 064908 (2013).
  • C. Wang, K. J. Chui, X. Wang, T. G. Lim, M. Yu, G. See, and G. Yu, "Passive devices fabrication on FOWLP and characterization for RF applications", In 2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 312-318 (2017).
  • A. Cardoso, S. Kroehnert, R. Pinto, E. Fernandes, and I. Barros, "Integration of MEMS/Sensors in Fan-Out wafer-level packaging technology based system-in-package (WLSiP)", In 2016 IEEE 18th Electronics Packaging Technology Conference (EPTC), 801-807 (2016).
  • Z. Chen, X. Zhang, S. P. S. Lim, S. S. B. Lim, B. L. Lau, Y. Han, M. C. Jong, S. Liu, X. Wang, and Y. Andriani, "Wafer level warpage modelling and validation for FOWLP considering effects of viscoelastic material properties under process loadings", In 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 1543-1549 (2019).
  • T. Uhrmann, J. Burggraf, and M. Eibelhuber, "Heterogeneous integration by collective die-to-wafer bonding", In 2018 International Wafer Level Packaging Conference (IWLPC), 1-7 (2018).
  • S. P. S. Lim, S. C. Chong, M. Z. Ding, and V. S. Rao, "Development of Chip-to-Wafer (C2W) bonding process for high density I/Os Fan-Out Wafer Level Package (FOWLP)", In 2016 IEEE 18th Electronics Packaging Technology Conference (EPTC), 435-440 (2016).
  • S. P. S. Lim, S. C. Chong, M. Z. Ding, and V. S. Rao, "Development of Chip-to-Wafer (C2W) bonding process for high density I/Os Fan-Out Wafer Level Package (FOWLP)", In 2016 IEEE 18th Electronics Packaging Technology Conference (EPTC), 435-440 (2016).
  • J. H. Lau and J. H. Lau, "Flip chip technology versus fowlp. Fan-Out Wafer-Level Packaging", 21-68 (2018).
  • Y. M. Lin, S. T. Wu, C. M. Wang, C. H. Lee, S. Y. Huang, A. Y. Lin, T. C. Chang, P. B. Lin, C. T. Ko, Y. H. Chen, and J. Su, "An RDL-first fan-out panel-level package for heterogeneous integration applications", In 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 1463-1469 (2019).
  • S. P. S. Lim, V. Chidambaram, N. Jaafar, and W. Seit, "Development of 2.5 D high density device on large ultra-thin active interposer", In 2019 IEEE 21st Electronics Packaging Technology Conference (EPTC), 247-252 (2019).