Journal of the Microelectronics and Packaging Society

The rapid advancement of 3D semiconductor packaging technology has led to a significant increase in the integration density of electronic components, emphasizing the importance of low-melting-point solders in preventing warpage and thermal damage post-reflow processing. Sn-58Bi (wt.%) solder has garnered considerable attention due to its low melting point and cost-effectiveness. However, its high brittleness, resulting in poor resistance to mechanical shock, remains a critical limitation. This comprehensive review systematically examines various strategies for mitigating the brittleness of Sn-58Bi solder. We focus on three key approaches: optimized alloy design, incorporation of nanocomposite materials, and implementation of innovative processing techniques for microstructure control and mechanical property enhancement. Through this analysis, we aim to propose practical solutions for substantially improving the performance of Sn-58Bi solder, thereby contributing to the advancement of next-generation 3D semiconductor packaging technologies. This study provides valuable insights into the current state of research and potential future directions in low-temperature solder development for advanced electronic packaging applications.

Sn-58Bi, Brittle, Solder, Low melting point, Packaging

The demand for power modules and next-generation WBG power semiconductors is surging owing to the growth of the electric vehicle market and the expansion of renewable energy. In particular, SiC power semiconductors require high-temperature die-attach materials to ensure thermal reliability, necessitating the development of Ag or Cu-based sinterbonding materials as alternatives to conventional solder. Compared to pressure-assisted processes, pressureless processes have significant industrial potential, however issues such as long processing times and low joint density must be addressed. Therefore, this paper reviews previously reported pressureless sinter-bonding methods for Ag and Cu fillers, categorizing them into chemical approaches, particle optimization, and other improvement methods. We analyze and compare the results and characteristics of these studies. The use of Ag nanoparticles in pressureless sinter-bonding has demonstrated rapid joint strength and dense joint formation based on accumulated research, suggesting high potential for future mass production applications. On the other hand, Cu-based pressureless sinter-bonding is still in its early research stages, however recent results showing successful sintering of ultrafine Cu nanoparticles in a nitrogen atmosphere indicate promising progress, suggesting that the development of Cu-based pressureless sinter-bonding technology will continue to advance actively

Power module, WBG semiconductor, SiC, Die-attach, Pressureless sinter-bonding, Nanoparticle

The rapid advancement of artificial intelligence (AI) technology has significantly increased the demand for large-scale data processing, highlighting the significant role of Optical I/O technology in semiconductor packaging. As AI models and high-performance computing (HPC) systems continue to grow in complexity, overcoming challenges such as the “Interconnect Wall” or “Power Wall,” which refer to interconnect bottlenecks, has become increasingly crucial. To address these challenges, Co-packaged Optics (CPO) has emerged as a promising solution, designed to enable the high-speed data transmission critical for AI and HPC systems. This paper will present Optical Interconnects, Silicon Photonics, and CPO as essential components for enhancing energy efficiency in next-generation AI and HPC implementations. In this paper, we introduce silicon photonics-based CPO technology for high-speed, low-power, and low-latency networks in next-generation HPC computing nodes designed to handle massive AI model operations. In particular, we examine the latest trends in advanced packaging—including Opto-chiplet packaging—built upon CPO and discuss its current status and future outlook.

Silicon photonics, Co-packaged optics (CPO), Advanced packaging, Optical I/O, Interconnect wall

AI semiconductors like GPUs, TPUs, and NPUs are crucial for deep learning models, with High Bandwidth Memory (HBM) enhancing performance. The HBM market is projected to grow annually by 46% from 2022 to 2029. To address challenges in semiconductor packaging, such as heat dissipation and signal interference, 3D-IC stacking and glass interposers with Through Glass Via (TGV) technology are emerging as key solutions. TGV improves thermal management, signal integrity, and cost efficiency. This paper discusses recent research trends in TGV manufacturing technologies, such as selective laser etching (SLE), functional layer deposition, and pulse electroplating, which are core technologies for enhancing the reliability and performance of AI semiconductors. SLE technology allows the formation of vias in glass by selectively removing material from a substrate using a laser and an etchant.

Through Glass Via (TGV), 2.5D Packaging, Etching, Electroplating

AI 알고리즘의 복잡성 증가로 고대역폭 메모리에서 실리콘 관통전극(through silicon via, TSV) 공정의 중요성이 부각되고 있다. 대표적인 TSV 형성 공정은 습식 식각과 건식 식각으로 나뉘며, 건식 식각 중 DRIE(deep reactive ion etching) 공정은 포토리소그래피(photolithography) 공정이 필요하고 스캘럽(scallop)모양 형성으로 인한 표면 거칠기 문제가 발생하는 단점이 있다. 반면, 레이저 드릴링(laser drilling)은 포토리소그래피 공정 없이 고종횡비 구현이 가능하다. 특히, 펨토초 레이저는 나노초 레이저에 비해 비열적 가공이 가능해 정밀한 가공에 유리하다. 그러나 펨토초 레이저의 단일 펄스 모드(single pulse mode)를 사용하여 비아홀(via hole)을 형성할 경우, 홀 내벽에 재응고층(recast layer), 잔여물(debris), 레이저 유도 주기적 표면 구조(laser induced periodic surface structures, LIPSS)가 형성되어 표면 거칠기가 증가한다. 이러한 거칠기는 도금 공정에서 도금성을 저하시키며, 전기 신호 전달 시 노이즈 증가와 성능 저하를 초래하게 된다. 본 연구는 펨토초 레이저의 버스트 모드(burst mode)를 활용하여 재응고층, 잔여물, LIPSS 생성을 제어함으로써 비아홀 가공의 최적 공정 조건을 제시하고자 한다.

Femtosecond laser, Burst mode, Sidewall roughness, LIPSS control, Through silicon via

Semiconductor packaging and testing are critical for ensuring the quality and performance of devices, especially as they become more miniaturized and integrated. The increasing demand for MEMS (Micro Electro Mechanical System)-based test socket technology has led to the widespread use of micro pins, designed for 300 μm pitch applications with diameters around 230 μm, in electrical testing. Due to their small size, traditional manual vision inspection methods face limitations in accuracy and efficiency. To address this, we designed an automated vision inspection system using the YOLO (You Only Look Once) algorithm to detect defects in micro pins. By capturing images of the spring part and measuring parameters such as length and width, we achieved a detection accuracy of 95%. This automated system significantly enhances accuracy and efficiency compared to manual methods, suggesting its potential application in semiconductor test equipment.

Semiconductor socket, Micro pin, Vision inspection, Defect detection, YOLO algorithm

Recently, with increasing demand for high-performance and multifunctional products in semiconductor market, the packaging technology has become critical to integrate a variety of components into a single system. Especially, wafer-level interposer and bridge fabrication methods are considered key components in this field. They can efficiently deliver electrical signals with high I/O density. However, excessive warpage can occur during the process due to thermal mismatch, leading to defects and reduced yield. In this paper, a finite element analysis was performed to predict the wafer warpage during the redistribution layer (RDL) process. The finite element model was created using one quarter of the entire wafer area and used shell elements with a composite type. The model was composed of a Si carrier and a RDL including through-via layer. Simulation results were compared for the different materials of through-via layer in RDL. The simulation was performed from 200°C to room temperature. Additionally, to analyze the effects of the number of RDL layers, simulation was conducted for both single and multi-layers. Simulation showed the significantly differences result depending on the material type of through-via layer and RDL thickness. These results enabled the identification of optimum combination to minimize the warpage and the temperature factor.

Warpage, Finite element method, Through-via layer, RDL

Semiconductor packaging technology has advanced in response to the increasing demands for high performance and miniaturization of electronic devices. Wire bonding and bump interconnection methods can detect defects during X-ray inspections in highly integrated semiconductor chips. However, inspection methods using CT scans result in longer scanning times, reducing productivity, and the increased radiation dose can lead to additional defects in the semiconductor chips. To address these issues, this study proposes a preprocessing method that combines deep learning networks, Fourier transform, and machine learning-based optimization techniques. The aim is to improve defect detection in semiconductor chips by removing background information that is not interesting from 2D X-ray projection images. The phantom data for the semiconductor chips was generated using MATLAB, and projection images were acquired using a GPU-based Geant4 simulator (GGEMS). Our proposed method effectively removed the background of semiconductor chip projection images while preserving critical details.

Semiconductor packaging, X-ray, Deep learning, Optimization

Recently, there has been a lot of research into glass as a material for interposer substrates used in 2.5D packaging technologies. Femtosecond lasers have been widely used to form TGV (through glass via) structures on glass interposers. However, damage caused by thermoelastic waves and shock waves during the TGV fabrication process using femtosecond lasers can limit the formation of vias with fine pitch, making it crucial to minimize damage during processing the damage caused by thermoelastic and shock waves during the processing of TGVs with femtosecond lasers is a challenge in forming closely spaced vias. In this study, we propose to reduce the via spacing while suppressing the damage caused by the single mode to the around of the via by using the burst mode in which the single pulse of the femtosecond laser is distributed and oscillated, and to analyze the mechanical properties around the via processed by single mode and burst mode through nanoindenter to suggest that the reason for the damage is related to the elastic modulus.

Femtosecond laser, Through glass via, Burst mode, Fine pitch

In this research, Fe-Ni alloy films were electroplated in the cell with different anode, DSA (inert anode) and Ni (soluble anode) to investigate the effect of anode type on the deposits and the baths. The deposits obtained from the Ni anode had higher Ni content than those from the DSA due to the increase in Ni²⁺ concentration of the baths, caused by Ni anode dissolution. The potential monitoring showed that the oxidation of Fe²⁺ to Fe³⁺ was the only reaction of DSA at the current density where Fe-Ni electroplating was conducted. Fe³⁺ formed at the DSA not only caused decrease in pH but increase in OCP of the baths. On the other hand, the pH and OCP of the bath using Ni anode changed slightly because the anodic potential during electroplating was insufficient to oxidize Fe²⁺ and form Fe³⁺.

Fe-Ni alloy, Electrodeposition, Inert anode, Soluble anode

The use and research of electrostatic chuck, a semiconductor equipment, are actively conducted to equalize the temperature applied to the wafer in the semiconductor manufacturing process. In this study, we propose a model that optimize the surface temperature uniformity through the design of a heater pattern among the parts of the electrostatic chuck. Electrostatic chuck consist of the two zone heater pattern, bonding layer, dielectric layer, plate and cooling path. The process environment assumed RIE and the heater pattern was heated by the applied voltage. According to the finite element method, we analyzed the effect that influence to temperature uniformity about model changed line width and Pigtail of heater pattern, and figured out the change of current density by shape of pattern. Finally, the proposed design model is expected to significantly improve the temperature uniformity of the electrostatic chuck surface and contribute to increasing the consistency of the semiconductor process. This study is expected important basic data for design optimization of ESC.

Electrostatic chuck, Heater pattern, Semiconductor process, Temperature uniformity, Finite element method

Modern electronic devices have evolved to be mechanically flexible, capable of withstanding repetitive deformation. This advancement necessitates ensuring the long-term reliability of metal interconnects, which are essential components in flexible electronic devices. In this study, we analyzed the fatigue behavior of U-shaped structures under tensile conditions, focusing on modifications at the interface between copper (Cu) films and polyimide (PI) substrates. The U-folding fatigue method, which involves complete flattening and bending of the sample compared to U-sliding fatigue, better simulates the actual fatigue deformation occurring during flexible device usage. We compared two adhesion enhancement methods: oxygen plasma treatment and chromium (Cr) adhesion layer introduction. The interfacial adhesion was quantitatively evaluated through nanoscratch tests, while fatigue failure mechanisms were investigated using electrical resistance measurements and microstructural analysis. Our findings revealed that under fatigue strain of 1.0%, the Cr adhesion layer exhibited the highest adhesion strength and showed significant improvement in fatigue resistance. This research provides essential guidance for enhancing the long-term reliability of flexible electronic devices by suggesting effective methods to improve fatigue resistance under practical usage conditions.

Flexible substrate, Metal interconnect, Adhesion, Reliability, Deformation mechanism

With the recent advancements in the wearable electronics industry, the field of flexible devices is rapidly expanding, leading to extensive research on their mechanical reliability. Generally, the properties of metal thin films are measured using nanoindentation techniques, but in the case of flexible devices, these properties tend to be underestimated due to the influence of the substrate. In this study, the contact area function was determined to measure the nanohardness as a function of depth for thin films deposited on flexible substrates. Copper (Cu) thin films with a thickness of 1 μm were deposited on polyimide (PI) substrates using sputtering, and nanoindentation experiments were conducted up to a maximum depth of 300 nm. Based on the assumption that the mechanical properties and the size of the indentation under the same load are identical, the contact area function for Cu/PI specimens was determined using results obtained from Cu films deposited on Si wafer substrates. The nanohardness as a function of depth was calculated to observe the substrate's influence at varying indentation depths. Furthermore, finite element analysis was performed to identify the range of stress fields beneath the indenter across the thin film and the substrate.

Nanohardness, Nanoindentation, Thin film, Flexible substrate