2025

Vol.32 No.1

Editorial Office

Current Issue

Journal of the Microelectronics and Packaging Society 2025;32(1):
Review of Continuum Mechanical Theories for the Thermal-Mechanical Reliability Analysis of Packages

Jeong-Hyeon Park1 , Hyunwoo Jung2 , and Eun-Ho Lee1,2,3,†

1 Department of Mechanical Engineering, Sungkyunkwan University, 2066, Seobu-ro, Jangan-gu, Suwon-si, Gyeonggi-do 16419, Republic of Korea 2 Department of Smart Fab. Technology, Sungkyunkwan University, 2066, Seobu-ro, Jangan-gu, Suwon-si, Gyeonggi-do 16419, Republic of Korea 3 Department of Intelligent Robotics, Sungkyunkwan University, 2066, Seobu-ro, Jangan-gu, Suwon-si, Gyeonggi-do 16419, Republic of Korea

Journal of the Microelectronics and Packaging Society Vol. 32, No. 1, pp. 1-12.

Abstract

Recent advancements in microelectronic packaging, such as chiplet architectures and heterogeneous integration, require dissimilar materials and complex interconnects, which affect thermal and mechanical behaviors, impacting semiconductor performance and reliability. To address these challenges, a systematic approach to analyzing thermal-mechanical behavior is essential. This includes methods like continuum mechanics theory, material property evaluation, and structural pattern consideration. While progress has been made in material evaluation and structural patterns, discussions on applying continuum mechanics theory to packaging remain limited. This paper reviews continuum mechanics, focusing on its application for analyzing thermal-mechanical coupling in packaging. It covers thermal-mechanical equilibrium laws, dissipation, and the importance of combining mechanical and thermal aspects in thermodynamic laws, as well as formulating material constitutive equations. Finally, it compares traditional analytical methods, simulations, and AI-based evaluations for applying continuum mechanics in package analysis. As packaging becomes more complex, understanding continuum mechanics will be crucial in optimizing and ensuring package reliability.

Keywords

Package, Thermal-mechanical behavior, Continuum mechanics, Numerical analysis, Artificial intelligence

Trends in Ultra-High Density Hybrid Bonding Stack Equipment Technology for High Bandwidth Memory (HBM) Semiconductors

Seung-Hwan Joo1,†, Jong-Su Lee2 , Myung-Ho Lee3 , Il-Shin Song4 , Young-Soo Kim2 , Kyoung-Rok Pyun1 , Seung-Ouk Roh5 , Goo-Sang Jung6 , and Byoung-Lok Jang1,†

1 Inha Manufacturing Innovation School, 36, Gaetbeol-ro, Yeonsu-gu, Incheon 21999, Republic of Korea 2 SH-INT, 412, Anaji-ro, Gyeyang-gu, Incheon 21129, Republic of Korea 3 TechL, 548, Gyeonggidong-ro, Hwaseong-si, Gyeonggi-do 18510, Republic of Korea 4 INNOBIZ, 2, Emtibeuibuk-ro 193beon-gil, Siheung-si, Gyeonggi-do 15118, Republic of Korea 5 LG Electronics, 222, LG-ro, Jinwi-myeon, Pyeongtaek-si, Gyeonggi-do 17709, Republic of Korea 6 Conception, 23-27, 4gongdan-ro 7-gil, Gumi-si, Gyeongsangbuk-do 39422, Republic of Korea

Journal of the Microelectronics and Packaging Society Vol. 32, No. 1, pp. 13-28.

Abstract

Recently, the transition to hybrid bonding has been an issue in the industry. This is because when the die to die gap is reduced to 10 µm, it is difficult to apply due to the technical limitations of conventional underfill, and it is essential to switch to hybrid bonding after HBM4 due to problems such as heat dissipation in logic die. In this review, we focus on the current status of hybrid bonders rather than the overall content of hybrid bonding as an industrial equipment. Unlike conventional BEOL systems, hybrid bonders are state-of-the-art systems that require extreme precision and require the development of core technologies that have been applied only to semiconductor majors, such as bondheads with 10-4 rotation precision and precise load control, nano-scale positioning accuracy stages and error correction algorithms, real-time bidirectional optics, and ISO-3 cleanliness environmental control (foreign matter/temperature). In addition, in order to understand the performance of the bonder, the alignment method of HBM, bonding quality test method by C-SAM, and bonding quality test method by bonding quality test by C-SAM, and the overall production of bonding equipment.

Keywords

Chiplet, Heterogeneous integration, Hybrid bonding, High bandwidth memory (HBM)

Recent Advances in Electroless Plating for Seed Layer Deposition on Glass Interposers

Yubin Kim, Seonwoo Kim, Suin Chae, Se-Hoon Park, Soobin Park, and Hyun Jin Nam

ICT Device Packaging Research Center, Korea Electronics Technology Institute (KETI), 25, Saenari-ro, Bundang-gu, Seongnam-si, Gyeonggi-do 13509, Republic of Korea

Journal of the Microelectronics and Packaging Society Vol. 32, No. 1, pp. 29-46.

Abstract

As the demand for high-performance electronic packaging continues to grow, glass interposers have emerged as a promising solution due to their excellent electrical insulation properties, low dielectric constant, and compatibility with high-density interconnections. However, the realization of a reliable seed layer on glass substrates remains a critical challenge, particularly in TGV (through-glass via) structures where conventional physical vapor deposition (PVD) techniques suffer from poor adhesion and high process costs. To overcome these limitations, electroless plating technology has been introduced as an alternative method that enables uniform metal deposition without requiring an external power source. This study systematically analyzes the feasibility and technical advantages of electroless plating for seed layer formation in glass interposers. Specifically, we compare Cu, Ni, and Ag electroless plating processes and evaluate various activation and surface modification techniques, including Pd-free catalytic layers, nano-silver activation, and silane-based adhesion promoters. Experimental results indicate that Pd-free Cu electroless plating provides high electrical conductivity while reducing material costs, Ni electroless plating offers superior corrosion resistance with improved adhesion through nano-silver catalysis, and Ag electroless plating achieves excellent conductivity while mitigating oxidation issues via silane functionalization. This study identifies electroless plating as a cost-effective alternative to PVD, enhancing adhesion and uniformity in TGV metallization.

Keywords

Electroless plating, Glass interposer, Surface modification, Seed layer formation

Warpage in Advanced Packaging: Challenges, Measurement Techniques, and Mitigation Strategies for Heterogeneous Integration

Sun-Woo Lee1,*, Min Sang Ju1,2,*, and Taek-Soo Kim1,2,†

1 Department of Mechanical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 291, Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea 2 Graduate School of Semiconductor Technology, Korea Advanced Institute of Science and Technology (KAIST), 291, Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea

Journal of the Microelectronics and Packaging Society Vol. 32, No. 1, pp. 47-60.

Abstract

As semiconductor technology moves beyond Moore’s Law, heterogeneous integration packaging has become pivotal for high-performance, miniaturized devices. Advanced packaging techniques—including 2.5D/3D integration, fan-out wafer-level packaging, and Si-bridge interconnects—significantly improve functionality by integrating multiple dies in one package. However, warpage has emerged as a critical thermomechanical challenge, causing misalignment, yield loss, and interconnect failures. Accurate warpage measurement and characterization methods are vital for mitigating these issues. Both experimental and simulation approaches assess warpage under various structures and process conditions. Research reveals warpage behaviors in wafer-level, panel-level, and Si-bridge-based packages, emphasizing strategies like material selection, structural design, and process optimization to reduce deformation. Emerging solutions—such as machine learning, realtime monitoring, and adaptive process control—aim to further enhance warpage management, improving manufacturability and reliability. By consolidating recent findings and identifying remaining challenges, this review offers insights into future directions for effective warpage reduction in advanced semiconductor packaging.

Keywords

Advanced packaging, Warpage, Si-bridge, 2.5D packaging, 3D integration, Warpage measurement

Research Trends in AI-Assisted Technology for Reliability Life Prediction of Wafer-Level Package

Geon-Joo Jeong1 , Dong Keun Lee2,†, and Kwang-Seok Kim1,†

1 Carbon & Light Materials Group, Korea Institute of Industrial Technology, 222, Palbok-ro, Deokjin-gu, Jeonju-si, Jeonbuk-do 54853, Republic of Korea 2 Specialized Machinery and Robotics Group, Korea Institute of Industrial Technology, 119, Jipyeongseonsandan 3-gil, Baeksan-myeon, Gimje-si, Jeonbuk-do 54325, Republic of Korea

Journal of the Microelectronics and Packaging Society Vol. 32, No. 1, pp. 61-74.

Abstract

Advanced packaging technologies are rapidly evolving to meet the semiconductor industry’s increasing demands for higher performance, miniaturization, and lower power consumption. Among these technologies, wafer-level packaging (WLP) has emerged as a key solution due to its superior capability in achieving compactness and enhanced performance. However, predicting the reliability life of WLP remains a significant challenge due to its complex structure and various environmental factors. Traditional reliability life prediction methods, such as physicsbased modeling and accelerated life testing, are limited by high costs and long time requirements. To address these limitations, artificial intelligence (AI), particularly machine learning (ML) algorithms, have gained significant attention. This study discusses recent trends in ML algorithms for reliability life prediction in advanced packaging, focusing on unsupervised learning, supervised learning, and hybrid learning approaches. Additionally, the paper provides insights into potential future research directions.

Keywords

Machine learning algorithms, Reliability life prediction, Supervised learning, Unsupervised learning, Hybrid learning, Advanced packaging

A Study on the Aerosol 3D Printing 10 μm Micro Patterning

Hui-Tae Kim1 , Ha-Neul Kim1 , Ka-Hyun Lee2 , Jong-Wook Shin3 , Kyoung-Rok Pyun1 , Jong-Su Lee4 , Byoung-Lok Jang1,†, and Seung-Hwan Joo1,†

1 Inha Manufacturing Innovation School, 36, Gaetbeol-ro, Yeonsu-gu, Incheon 21999, Republic of Korea 2 Materials Science and Engineering, Inha University, 100, Inha-ro, Michuhol-gu, Incheon 22212, Republic of Korea 3 Chemical Engineering, Inha University, 100, Inha-ro, Michuhol-gu, Incheon 22212, Republic of Korea 4 SH Global, 412, Anaji-ro, Gyeyang-gu, Incheon 21129, Republic of Korea

Journal of the Microelectronics and Packaging Society Vol. 32, No. 1, pp. 75-83.

Abstract

To overcome the limitations of conventional inkjet printing technology in fine patterning, we designed and developed an aerosol 3D printing system (A3DP) using pneumatics. The A3DP system consists of a pneumatic control unit, an atomizer, a virtual impactor, and a nozzle head using sheath gas. In this study, we aimed to investigate the effect of process parameters on micro patterning in the A3DP system using pneumatics, and print 10 µm micro patterning on the substrate in this system. In this paper, the effects of process parameters such as stand-off distance, sheath gas flow rate, and printing speed on micro patterning were experimented, and the results showed that a stand-off distance of 1 mm to 5 mm and a focusing ratio (FR) of 4 to 6 are suitable for micro patterning. Based on the above, we confirmed the possibility of achieving 10 µm micro patterning on the pneumatic A3DP, which is difficult to achieve with conventional inkjet printing, by ejecting line widths of 33.07 µm with a 300 µm nozzle, 23.75 µm with a 200 µm nozzle, and 16.56 µm with a 100 µm nozzle. ANSYS Fluent analysis indicated a need for improvements to address overspray and flow deviation.

Keywords

Aerosol, Aerosol 3D printing system, Semiconductor, Ink jet printing

Effect of Iron Ions (Fe2+ and Fe3+) on the Decomposition of Organic Additives during Copper Electrodeposition

Kyungtae Kim1,2, Min Ki Park3 , Yeunseok Ha3 , Chanyoung Jeong2,†, and Seunghoe Choe3,†

1 Surface & Nano Materials Division, Korea Institute of Materials Science (KIMS), 797, Changwon-daero, Seongsan-gu, Changwon-si, Gyeongsangnam-do 51508, Republic of Korea 2 Department of Advanced Materials Engineering, Dong-eui University, 176, Eomgwang-ro, Busanjin-gu, Busan 47340, Republic of Korea 3 Department of Advanced Materials Engineering, Tech University of Korea, 237, Sangidaehak-ro, Siheung-si, Gyeonggi-do 15073, Republic of Korea

Journal of the Microelectronics and Packaging Society Vol. 32, No. 1, pp. 84-91.

Abstract

In this study, the effect of iron ions on the decomposition of organic additives during copper electrodeposition was examined. When either ferrous (Fe2+) or ferric ion (Fe3+) was added to the plating bath, the decompositions of co-added additives (bis-(3-sulfopropyl)-disulfide and polyethylene glycol) were clearly retarded under both electrolytic and open-circuit conditions. The retardation of additive decomposition could be attributed to the removal of reactive species (Cu+ and Cl2) by redox reaction of Fe2+ and Fe3+. These results show that the Fe2+/Fe3+ redox couple could increase bath lifetime by inhibiting additive decomposition, even though it is Fenton’s reagent.

Keywords

Copper, Electrodeposition, Organic additive, Decomposition, Ferric ion, Ferrous ion

Automatic Detailed Region of Interest Model for Real-Time Semiconductor Package Defect Detection

Seungtaek Lim1 , Youngjin Park2 , Wonyong Choi3 , and Keejun Han1,†

1 School of Computer Engineering, Hansung University, 116, Samseongyo-ro 16-gil, Seongbuk-gu, Seoul 02876, Republic of Korea 2 R&D Center, DeepSeers, 21, Baekbeom-ro 31-gil, Mapo-gu, Seoul 04147, Republic of Korea 3 R&D Center, Genesem, 24, Songdogwahak-ro 84beon-gil, Yeonsu-gu, Incheon 21984, Republic of Korea

Journal of the Microelectronics and Packaging Society Vol. 32, No. 1, pp. 100-113.

Abstract

As high-performance semiconductor packaging technologies such as 2.5D and 3D packaging along with the advancement of artificial intelligence (AI) have emerged with more complex packaging designs, the number of areas that need to be inspected in the package continues to increase. As a result, a rule-based defect inspection system that defines inspection areas and sets thresholds manually is time-consuming and error-prone. To solve this problem, this study proposes a method to automatically extract the region of interest (ROI) from actual quad flat no-lead (QFN) and ball grid array (BGA) package images using deep learning models. In this study, we analyzed the effect of the amount on the model performance using the YOLOv8, YOLOv9, YOLOv10, and YOLOv11 models, which are commonly used in real-time object detection, and showed that the performance of automatic detailed ROI extraction can improve with small datasets through data augmentation and preprocessing techniques. In addition, it was proved that the deep learning model can detect important elements in semiconductor packages well with high accuracy by considering various lighting change conditions in the industrial site. This study will be used as important basic data to improve the automation and efficiency of the semiconductor package inspection system.

Keywords

Semiconductor package inspection, Defect detection, ROI extraction, Deep learning, Machine vision

A Study on the Fabrication of Ti-Based MXene and Sn-58Bi Nano Metal Composites and Their Soldering Properties for Electronic Packaging

Jae Jeong Lee1 , Han Xue1 , Hye Ri Go2 , Yoon Chul Sohn2 , and Yun Sung Woo1,†

1 Department of Materials Science and Engineering, Dankook University, 119, Dandae-ro, Dongnam-gu, Cheonan-si, Chungcheongnam-do 31116, Republic of Korea 2 Department of Welding & Joining Science Engineering, Chosun University, 309, Pilmun-daero, Dong-gu, Gwangju 61452, Republic of Korea

Journal of the Microelectronics and Packaging Society Vol. 32, No. 1, pp. 114-122.

Abstract

As semiconductor chips continue to become smaller and more functional, there is an increasing demand for more robust packaging materials that can protect the chips and enhance their performance. In particular, the development of low-temperature solder materials with excellent thermal and mechanical reliability is of great importance. Therefore, in this study, a lead-free Sn-58Bi low-temperature solder material reinforced with Ti3C2Tx was developed using the solid-state mixing method of ball milling. The effects of Ti3C2Tx addition on the microstructure and mechanical strength of the Ti3C2Tx/Sn-58Bi nano metal composite were investigated. The experimental results showed that as the Ti3C2Tx content increased, the microstructure of the Sn-58Bi alloy became progressively finer, and the Vickers hardness increased. The nano metal composite with 0.13 wt.% Ti3C2Tx exhibited an approximately 31% increase in hardness. Meanwhile, the thickness of intermetallic compounds (IMCs) formed at the interface between the solder and the substrate made from Ti3C2Tx/Sn-58Bi nano metal composite powder gradually decreased as the Ti3C2Tx content increased. These results suggest that the Ti3C2Tx/Sn-58Bi nano metal composite developed in this study can be applied as an electronic packaging material with excellent thermal and mechanical reliability.

Keywords

Ti3C2Tx, SnBi solder, Ball milling, Composite, Packaging

Error Correction

Journal of the Microelectronics and Packaging Society Vol. 32, No. 1, pp. 123-123.

Abstract

Keywords