Journal of the Microelectronics and Packaging Society

Recently, with increasing demand for high-performance and multifunctional products in semiconductor market, the packaging technology has become critical to integrate a variety of components into a single system. Especially, wafer-level interposer and bridge fabrication methods are considered key components in this field. They can efficiently deliver electrical signals with high I/O density. However, excessive warpage can occur during the process due to thermal mismatch, leading to defects and reduced yield. In this paper, a finite element analysis was performed to predict the wafer warpage during the redistribution layer (RDL) process. The finite element model was created using one quarter of the entire wafer area and used shell elements with a composite type. The model was composed of a Si carrier and a RDL including through-via layer. Simulation results were compared for the different materials of through-via layer in RDL. The simulation was performed from 200°C to room temperature. Additionally, to analyze the effects of the number of RDL layers, simulation was conducted for both single and multi-layers. Simulation showed the significantly differences result depending on the material type of through-via layer and RDL thickness. These results enabled the identification of optimum combination to minimize the warpage and the temperature factor.

Keywords Warpage, Finite element method, Through-via layer, RDL