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KCI Accredited Journals KCI 등재지
KCI Impact Factor 0.54
Journal of the Microelectronics and Packaging Society 2023;30(3):40-50. Published online: Nov, 9, 2023
DOI : doi.org/10.6117/kmeps.2023.30.3.040
Recently, the number of components of smartphones increases rapidly, while the PCB size continuously decreases. Therefore, 3D technology with a stacked PCB has been developed to improve component density in smartphone. F or the stacked PCB, it is very important to obtain solder bonding quality between PCBs. We investigated the effects of the properties, thickness, and number of layers of interposer PCB and sub PCB on warpage of PCB through experimental and numerical analysis to improve the reliability of the stacked PCB. The warpage of the interposer PCB decreased as the thermal expansion coefficient (CTE) of the prepreg decreased, and decreased as the glass transition temperature (Tg) increased. However, if temperature is 240°C or higher, the reduction of warpage is not large. As FR-5 was applied, the warpage decreased more compared to FR-4, and the higher the number and thickness of the prepreg, the lower the warpage. For sub PCB, the CTE was more important for warpage than Tg of the prepreg, and increase in prepreg thickness was more effective in reducing the warpage. The shear tests indicated that the dummy pad design increased bonding strength. The tumble tests indicated that crack occurrence rate was greatly reduced with the dummy pad.
Keywords Stacked PCB, Interposer, Prepreg, Warpage, Reliability