2024

Vol.30 No.4

Editorial Office

Review

  • Journal of the Microelectronics and Packaging Society
  • Volume 30(3); 2023
  • Article

Review

Journal of the Microelectronics and Packaging Society 2023;30(3):40-50. Published online: Nov, 9, 2023

Warpage and Solder Joint Strength of Stacked PCB using an Interposer

  • Kipoong Kim1 , Yuhwan Hwangbo1 , and Sung-Hoon Choa2,†
    1 Department of Nano IT Fusion Engineering, Seoul National University of Science and Technology, 232, Gongneung-ro, Nowon-gu, Seoul, Republic of Korea, 2 Department of Intelligent Semiconductor Engineering, Seoul National University of Science and Technology, 232, Gongneung-ro, Nowon-gu, Seoul, Republic of Korea
Abstract

Recently, the number of components of smartphones increases rapidly, while the PCB size continuously decreases. Therefore, 3D technology with a stacked PCB has been developed to improve component density in smartphone. F or the stacked PCB, it is very important to obtain solder bonding quality between PCBs. We investigated the effects of the properties, thickness, and number of layers of interposer PCB and sub PCB on warpage of PCB through experimental and numerical analysis to improve the reliability of the stacked PCB. The warpage of the interposer PCB decreased as the thermal expansion coefficient (CTE) of the prepreg decreased, and decreased as the glass transition temperature (Tg) increased. However, if temperature is 240°C or higher, the reduction of warpage is not large. As FR-5 was applied, the warpage decreased more compared to FR-4, and the higher the number and thickness of the prepreg, the lower the warpage. For sub PCB, the CTE was more important for warpage than Tg of the prepreg, and increase in prepreg thickness was more effective in reducing the warpage. The shear tests indicated that the dummy pad design increased bonding strength. The tumble tests indicated that crack occurrence rate was greatly reduced with the dummy pad.

Keywords Stacked PCB, Interposer, Prepreg, Warpage, Reliability

REFERENCES
  • H.-H. Loh and M.-S. Lu, "Printed circuit board inspection using image analysis", IEEE Transactions on industry applications, 35(2), 426-432 (1999).
  • M. Korobkov, F. Vasilyev, and V. Mozharov, "A comparative analysis of printed circuit boards with surface-mounted and embedded components under natural and forced convection", Micromachines, 13(4), 634 (2022).
  • Fukazawa, N., A. Murakawa, W. Fujikawa, and J. Shirakami, "Novel Silver-seed Semi-Additive Process for High Quality Circuit Formation", 2019 International Conference on Electronics Packaging (ICEP), 173-176, IEEE, (2019).
  • Y. Kitahara and J. Kang, "Ultra-fine patterning technology by utilizing nano-silver catalysts in MSAP", 2018 International Conference on Electronics Packaging and iMAPS All Asia Conference (ICEP-IAAC), 112-115, IEEE, (2018).
  • F. Liu, J. Lu, V. Sundaram, D. Sutter, G. White, D. F. Baldwin, R. R. Tummala et al., "Reliability assessment of microvias in HDI printed circuit boards", IEEE Transactions on Components and Packaging Technologies, 25(2), 254-259 (2002).
  • G. Kim, D. Kwon, "Warpage Analysis during Fan-Out Wafer Level Packaging Process using Finite Element Analysis", Journal of Nanoscience and Nanotechnology, 21(5), 2987-2991 (2017).
  • J.-M. Koo, C.-Y. Lee, and S.-B. Jung, "Effect of Reflow Number on Mechanical and Electrical Properties of Ball Grid Array (BGA) Solder Joints", J. Microelectron. Packag. Soc., 14(4), 71-77 (2007).
  • D.-W. Park, M.-H. Yu, and H. Kim, "A Study on Effect of Pad Design on Assembly and Adhesion Reliability of Surface Mount Technology (SMT)", J. Microelectron. Packag. Soc., 29(3), 31-35 (2022).
  • H.-S. Lee, H. C. Kwon, "Effectiveness of Residual Stress on Forming Copper Patterns of Printed Circuit Board", Materials Science Forum, 654-656, 2716-2719 (2010).
  • S. Chung, G. Heo, J. Kwak, S. Oh, Y. Lee, C. Kang, and T. Lee, "Development of PCB design guide and PCB deformation simulation tool for slim PCB quality and reliability", 2013 IEEE 63rd Electronic Components and Technology Conference, 2157-2162, IEEE, (2013).
  • D. Park, D. Jung, and T. Oh, "Warpage Characteristics Analysis for Top Packages of Thin Package-on-Packages with Progress of Their Process Steps", J. Microelectron. Packag. Soc., 21(2), 65-70, (2014).
  • Y. Yang, "Discussion and failure analysis of PCB warpage", 2019 20th International Conference on Electronic Packaging Technology(ICEPT), 1-3, IEEE, (2019).
  • K.-H. Kim, H. Lee, J.-W. Jeong, J.-H. Kim, and S.-H. Choa, "Numerical Analysis of Warpage and Stress for 4-layer Stacked FBGA Package", J. Microelectron. Packag. Soc., 19(2), 7-15, (2012).
  • O. Albrecht, H. Wohlrabe, K. Meier, "Impact of warpage effects on quality and reliability of solder joints", 2019 42nd International Spring Seminar on Electronics Technology (ISSE), 1-6, IEEE, (2019).
  • M. Rayasam, T.B. Thompson, G. Subbarayan, C. Gurumurthy, and J. Wilcox, "A model for assessing the shape of solder joints in the presence of PCB and package warpage", Journal of Electronic Packaging, 128(3), 184 (2006).
  • T. Lee, J. Lee, I. Jung, "Finite element analysis for solder ball failures in chip scale package", Microelectronics Reliability, 38, 1941-1947 (1998).
  • S. J. Oon, K. S. Tan, T. Y. Tou, S. S. Yap, C. S. Lau, and Y. T. Chin, "Warpage studies of printed circuit boards with Shadow Moire and simulations", 2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT), 1-5, IEEE, (2018).
  • S. Chung, S. Oh, T. Lee, and M. Park, "Thermo-mechanical analyses of printed board assembly during reflow process for warpage prediction", 2014 15th International Conference on Thermal, Mechanical and Mulit-Physics Simulation and Experiments in Microelectronics and Microsystems (Euro-SimE), 1-5, IEEE, (2014).
  • J. Cooper and D. Kwak, "Reliability Testing of Consumer Products", 2020 Pan Pacific Microelectronics Symposium (Pan Pacific), 1-9, IEEE, (2020).