2024

Vol.31 No.2

Current Issue Archives
Search
Advanced Search
Editorial Office

Review

  • Journal of the Microelectronics and Packaging Society
  • Volume 31(1); 2024
  • Article

Review

Journal of the Microelectronics and Packaging Society 2024;31(1):35-42. Published online: May, 10, 2024

PDF Full Text XML

DOI : doi.org/10.6117/kmeps.2024.31.1.035

Properties of Cu Pillar Bump Joints during Isothermal Aging

  • Eun-Su Jang1 , Eun-Chae Noh1 , So-Jeong Na2 , and Jeong-Won Yoon1,†
    1Department of Advanced Materials Engineering, Chungbuk National University, Chungdae-ro, Seowon-gu, Cheongju, Chungbuk 28644, Korea, 2Welding and Joining R&D Group, Korea Institute of Industrial Technology (KITECH), 156 Gaetbeol-ro, Yeonsu-Gu, Incheon 21999, Korea
Corresponding author E-mail: jwyoon@chungbuk.ac.kr
Abstract

Recently, with the miniaturization and high integration of semiconductor chips, the bump bridge phenomenon caused by fine pitches is drawing attention as a problem. Accordingly, Cu pillar bump, which can minimize the bump bridge phenomenon, is widely applied in the semiconductor package industry for fine pitch applications. When exposed to a high-temperature environment, the thickness of the intermetallic compound (IMC) formed at the joint interface increases, and at the same time, Kirkendall void is formed and grown inside some IMC/Cu and IMC interfaces. Therefore, it is important to control the excessive growth of IMC and the formation and growth of Kirkendall voids because they weaken the mechanical reliability of the joints. Therefore, in this study, isothermal aging evaluation of Cu pillar bump joints with a CS (Cu+ Sn-1.8Ag Solder) structure was performed and the corresponding results was reported.

Keywords Cu pillar bump, Intermetallic compound, Kirkendall void, Aging, Reflow soldering

REFERENCES
  • K. H. K. Frank, J. Lee, F. L. Chien, R. Lee, C. Mao, and J. Lau, "Electromigration performance of Cu pillar bump for flip chip packaging with bump on trace by using thermal compression bonding", 2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 6897267, 56-61(2014).
  • Y. Wang, K. H. Lu, J. lm, and P. S. Ho, "Reliability of Cu pillar bumps for flip-chip packages with ultra low-k dielectrics", 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC), 5490819, 1404-1410(2010).
  • M. Y. Kim, S. K. Lim, and T. S. Oh, "Thermal Cycling and High Temperature Storage Reliabilities of the Flip Chip Joints Processed Using Cu Pillar Bumps", J. Microelectron. Packag. Soc., 17(3), 27-32(2010).
  • M. Gerber, C. Beddingfield, S. O'Connor, M. Yoo, M. J. Lee, D. B. Kang, and S. S. Park, "Next Generation Fine Pitch Cu Pillar Technology - Enabling Next Generation Silicon Nodes", 2011 IEEE 61st electronic components and technology conference (ECTC), 5898576, 613-618(2011).
  • J. S. Ha, J. P. Jung, and T. S. Oh, "Effects of Intermetallic Compounds Formed during Flip Chip Process on the Interfacial Reactions and Bonding Characteristics", J. Microelectron. Packag. Soc., 19(2), 35(2012).
  • J. Y. Choi, M. Y. Kim, S. K. Lim, and T. S. Oh, "Flip Chip Process for RF Packages Using Joint Structures of Cu and Sn Bumps", J. Microelectron. Packag. Soc., 67(2009).
  • G. T. Lim, B. J. Kim, K. W. Lee, M. J. Lee, Y. C. Joo, and Y. B. Park, "Study on the Intermetallic Compound Growth and Interfacial Adhesion Energy of Cu Pillar Bump", J. Microelectron. Packag. Soc., 15(4), 17-24(2008).
  • J. C. Liao, A. Liao, S. Peng, G. T. Lin, T. Lu, and S. Chen, "Die Bonding with Non-Clean Flux in Fine Pitch Copper Pillar Bump Study and Reliability Performance for 2.5D IC Package", IEEE 66th Electronic Components and Technology Conference (ECTC), 7545664, 1786-1790(2016).
  • E. C. Noh, H. W. Lee, and J. W. Yoon, "Recent Advances in Fine Pitch Cu Pillar Bumps for Advanced Semiconductor Packaging", J. Microelectron. Packag. Soc., 30(3), 1-10(2023).
  • G. T. Lim, J. H. Lee, B. J. Kim, K. W. Lee, M. J. Lee, Y. C. Joo, and Y. B. Park, "Effect of Thermal Aging on the Intermetallic compound Growth kinetics in the Cu pillar bump", J. Microelectron. Packag. Soc., 14(4), 15-20(2007).
  • G. T. Lim, B. J. Kim, K. Lee, J. Kim, Y. C. Joo, and Y. B. Park, "Temperature Effect on Intermetallic Compound Growth Kinetics of Cu Pillar/Sn Bumps", J. Electron. Mater., 38, 2228-2233(2009). https://doi.org/10.1007/s11664-009-0922-0
  • T. Wang, F. Tung, L. Foo, and V. Dutta, "Studies on a Novel Flip-Chip Interconnect Structure-Pillar Bump", 2001 Proceedings. 51st Electronic Components and Technology Conference (ECTC), 927911, 945-949(2001).
  • I. N. Jang, J. H. Park, and Y. S. Ahn, "Mechanical Characteristic Evaluation of Sn-Ag-Cu Lead Free Solder Ball Joint on The Pad Geometry", J. Microelectron. Packag. Soc., 17(2), 41-47(2010).
  • K. S. Kim, S. H. Huh, and K. Suganuma, "Effects of intermetallic compounds on properties of Sn-Ag-Cu lead-free soldered joints", J. Alloys Compd., 226-236(2003).
  • S. Chada, R. A. Fournelle, W. Laub, and D. Shangguan, "Copper Substrate Dissolution in Eutectic Sn-Ag Solder and Its Effect on Microstructure", J. Electron. Mater., 29, 1214-1221(2000). https://doi.org/10.1007/s11664-000-0015-6
  • M. H. Jeong, J. M. Kim, S. H. Yoo, C. W. Lee, and Y. B. Park, "Effect of PCB Surface Finishes on Intermetallic Compound Growth Kinetics of Sn-3.0Ag-0.5Cu Solder Bump", J. Microelectron. Packag. Soc., 17(1), 81-88(2010).
  • S. K. Kang, D. Y. Shih, N.Y. Donald, W. Henderson, T. Gosselin, A. Sarkhel, and W. K. Choi, "Ag3Sn Plate Formation in the Solidification of Near-Ternary", JOM., 55(6), 61-65(2003). https://doi.org/10.1007/s11837-003-0109-8
  • D. Xie, D. Shangguan, and H. Kroener, "Pad Cratering Evaluation of PCB", APEX., 2722-2750(2010).
  • M. H. Heo, D. H. Lee, M. S. Jeong, and J. W. Yoon, "Effects of shear test temperatures and conditions on mechanical properties of Sn-Ag flip-chip solder bumps", J Mater Sci Mater Electron., 33(13), 1003-1012(2022).