2024

Vol.31 No.2

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  • Journal of the Microelectronics and Packaging Society
  • Volume 31(2); 2024
  • Article

Review

Journal of the Microelectronics and Packaging Society 2024;31(2):16-22. Published online: Jul, 25, 2024

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DOI : doi.org/10.6117/kmeps.2024.31.2.016

Research on Process Technology of Molded Bridge Die on Substrate (MBoS) for Advanced Package

  • Jaeyoung Jeon, Donggyu Kim, Wonseok Choi, Yonggyu Jang, Sanggyu Jang, and Yong-Nam Koh†
    HANA Micron Ins., 77, Yeonamyulgeum-ro, Eumbong-myeon, Asan-si, Chungcheongnam-do, Republic of Korea
Corresponding author E-mail: yongnamkoh@hanamicron.co.kr
Abstract

With advances of artificial intelligence (AI) technology, the demand is increasing for high-end semiconductors in various places such as data centers. In order to improve the performance of semiconductors, reducing the pitch of patterns and increasing density of I/Os are required. For this issue, 2.5dimension(D) packaging is gaining attention as a promising solution. The core technologies used in 2.5D packaging include microbump, interposer, and bridge die. These technologies enable the implementation of a larger number of I/Os than conventional methods, enabling a large amount of information to be transmitted and received simultaneously. This paper proposes the Molded Bridge die on Substrate (MBoS) process technology, which combines molding and Redistribution Layer (RDL) processes. The proposed MBoS technology is expected to contribute to the popularization of next-generation packaging technology due to its easy adaption and wide application areas.

Keywords Molding, 2.5D Packaging, Bridge Die, Interposer

REFERENCES
  • R. James, “The Future of the High-Performance Semiconductor Industry and Design”, Proc. 2022 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, 65, 32-35 (2022).
  • C. C. Wang, Y. C. Huang, T. K. Chang, and Y. Lin, “A new semiconductor package design flow and platform applied on high density fan-out chip”, Proc. 2021 71st Electronic Components and Technology Conference (ECTC), San Diego, 112-117 (2021).
  • P. Y. Lin, M. C. Yew, S. S. Yeh, S. M. Chen, C. H. Lin, C. S. Chen, and S. P. Jeng, “Reliability Performance of Advanced Organic Interposer (CoWoS®-R) Packages”, Proc. 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, 723-728 (2021).
  • R. Mahajan, Z. Qian, R. S. Viswanath, S. Srinivasan, K. Aygün, W. L. Jen, and A. Dhall, “Embedded multidie interconnect bridge—A localized, high-density multichip packaging interconnect”, IEEE Trans. Compon. Packaging Manuf. Technol., 9(10), 1952-1962 (2019).
  • E. -C. Noh, H. -W. Lee, J. -W. Yoon, “Recent Advances in Fine Pitch Cu Pillar Bumps for Advanced Semiconductor Packaging”, J. Microelectron. Packag. Soc., 30(3), 1-10 (2023).
  • M. Suh, “Technology Trends of Semiconductor Package for ESG”, Journal of the Microelectronics and Packaging Society, 3(30), 35-39 (2023).
  • A. Shehabi, et al., “United states data center energy usage report”, Energy Technologies Area, Berkeley Lab, US (2016).
  • B. Hill, “Micron Announces HBM next As Eventual Replacement for HBM2e In High-End GPUs”, HotHardware, (2020) from https://hothardware.com/news/
  • K. J. Han, “System Packaging Technology Development Trends”, KIEES Magazine: Electromagnetic Technology, 31(1), 31-40 (2020).
  • G. Duan, Y. Kanaoka, R. McRee, B. Nie, and R. Manepalli, “Die Embedding Challenges for EMIB Advanced Packaging Technology”, 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 1-7 (2021).
  • R. Mahajan, R. Sankman, N. Patel, D.-W. Kim, K. Aygun, Z. Qian, Y. Mekonnen, I. Salama, S. Sharan, D. Iyengar, and D. Mallik, “Embedded Multi-Die Interconnect Bridge (EMIB) – A High Density High Bandwidth Packaging Interconnect”, 2016 IEEE 66th ECTC Conference, 557-565 (2016).
  • A. C. Durgun, Z. Qian, K. Aygun, R. Mahajan, T. T. Hoang, and S. Y. Shumarayev, “Electrical Performance Limits of Fine Pitch Interconnects for Heterogeneous Integration”, 2019 IEEE 69th ECTC conference, 667-673 (2019).
  • R. Mahajan, Z. Qian, R. S. Viswanath, S. Srinivasan, K. Aygün, W.-L. Jen, S. Sharan, and A. Dhall, “Embedded Multidie Interconnect Bridge – A Localized, High-Density Multichip Packaging Interconnect”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, 9(10), 1952-1962 (2019).
  • H. J. Kim, J. P. Jung, “Artificial Intelligence Semiconductor and Packaging Technology Trend.” J. Microelectron. Packag. Soc., 30(3), 11-19 (2023).
  • Jiang, Feng, et al., “Wafer level warpage characterization for backside manufacturing processes of TSV interposers”, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 6897532 (2014).
  • G. Kim, D. Kwon, “Warpage Analysis during Fan-Out Wafer Level Packaging Process using Finite Element Analysis”, J. Microelectron. Packag. Soc., 25(1), 41-45 (2018).
  • K. Kim, Y. Hwangbo, S. H. Choa, “Warpage and Solder Joint Strength of Stacked PCB using an Interposer”, J. Microelectron. Packag. Soc., 30(3), 40-50 (2023).
  • C.-C. Lee, et al., “An overview of the development of a GPU with integrated HBM on silicon interposer”, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 1439-1444 (2016).