Journal of the Microelectronics and Packaging Society

With shrinking form factor and improving performance of electronic packages, high input/output (I/O) density is considered as an important factor. Fan out wafer-level packaging (FO-WLP) has been paid great attention as an alternative. However, FO-WLP is vulnerable to warpage during its manufacturing process. Minimizing warpage is essential for controlling production yield, and in turn, package reliability. While many studies investigated the effect of process and design parameters on warpage using finite element analysis, they did not take uncertainty into consideration. As parameters, including material properties, chip positions, have uncertainty from the point of manufacturing view, the uncertainty should be considered to reduce the gap between the results from the field and the finite element analysis. This paper focuses on the effect of uncertainty of Young’s modulus of chip on fan-out wafer level packaging warpage using finite element analysis. It is assumed that Young’s modulus of each chip follows the normal distribution. Simulation results show that the uncertainty of Young’s modulus affects the maximum von Mises stress. As a result, it is necessary to control the uncertainty of Young’s modulus of silicon chip since the maximum von Mises stress is a parameter related to the package reliability.

Keywords Fan out wafer level package, Warpage, Uncertainty, Finite element analysis